PROTO ideas for a GVM container

Today we are talking about PROTO ideas on the GOYA transport system and VAVILON cores for the GVM container.

Greetings, dear readers of the blog! Today we are talking about PROTO ideas on the GOYA transport system and VAVILON cores for the GVM container. Have a productive reading!

Step № 1: Accelerators for the processing of transport packages.

Scientific task:

How will we achieve the theoretical processing limit of 150 Mpps (million packets per second) for short packets for the 100G port?
Consider packet parser options for the 100G and 400G technologies (in the future).

Decision:

Optimal selection of PPE cores (packet processing engine).

To process packets at a speed of 100G, you need to implement a massive parallelism.

For example, in the QuantumFlow processor 40 cores from Tensilica are implemented. Each core has 4 threads. Thus, 160 packets are processed simultaneously.

For each PPE, you need to implement the hardware assist function.

What is PPE?

[http://web.engr.oregonstate.edu/~qassim/index_files/Final_ECE570_ASP_2012_Project_Report.pdf]

PPE are implemented together with accelerators:

PPE can access hardware feature acceleration of network address and prefix lookups, hash lookups, WRED, Traffic Policers, range lookups, and TCAM for advanced classification and access-control-list (ACL) acceleration as it processes packets.

[http://www.cisco.com/en/US/prod/collateral/routers/ps9343/solution_overview_c22-448936.html]

Expanders:

Expanders (accelerators) for processing packets – creating expanders for K 64-SMP.

Extensions for optimal packet processing can be useful for creating a specialized network processor (using the Cisco QuantumFlow model) and further development of the GONT Chain routers.

Stages:

  1. GONT develops an architecture and a simulator for specialized packet processing instructions (within the SUPER-KANT module).
  2. Analysis of the optimum realizability of the expander (VAVILON core).
  3. Functional verification.
  4. GONT interacts with XXX to implement RTL code and simulate RTL within the testbench.
  5. Writing of articles and patents, registration of IP.

What is the essence of technology?

The basis of technology:

1) Realization of optimized access to memory using Streamer – by analogy with graphics processors.
2) Implementation of specialized instructions for processing packages – accelerators.
3) Implementation of pipeline processing of transport packages, provided that a security coprocessor is available.

The extensions (accelerators) that will be implemented (using the Cisco PPE model):

  • accelerator for searching the packet start code (several bytes) in the transport stream
  • search accelerator package ID
  • packet parsing accelerator
  • CRC check accelerator
  • accelerator memcopy

Step № 2: Implementation of a hybrid transport system (for a multifunction switch).

Dataflow scenarios:

  1. DMA engine
  2. Host CPU
  3. SATA/USB
  4. Ethernet
  5. Reading of saved packages
  6. Encrypting and saving transport packets

Thank you for attention! See you in the next articles.
GONT

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